Coming to the last and final section of this article, am sure you are well aware that verification does pose some problem to Embedded designers. This section deals with the methods to tackle them. I will try and keep it simple so its easy to comprehend.
Current-based simulation
Active MOS devices are intrinsically current-based devices and a current-based model reflects this behavior significantly better than a voltage-based model. While a voltage-based model provides important information about transistor behavior, it has several drawbacks in terms of accuracy for current measurements, stability in simulations and size of the resulting matrix.
Current-based models are not only as accurate as Spice or Spice-like models, but they also simplify the topological structure of the equivalent circuits. This greatly improves the solution of non-linear equations and matrices. Additionally, current-based models are very efficient in device representation and require less memory than voltage-based models. This helps a great deal in addressing the large physical memory requirements when simulating large embedded memories.
Multi-engine architecture
An embedded memory circuit profile is unique in that it consists of digital, analog and mixed-signal blocks that closely interact with each other. Other features are the large replication of circuit structures and the small amount of active circuitry at any given clock cycle. The memory in itself can be decomposed into basic transistors, bit-cell blocks, decode blocks, interconnect structures and multiple other design entities that each share a unique simulation profile.
When considering a circuit for simulation, traditional fast Spice simulators use one monolithic engine to tackle all the varied elements in the circuit. This is inefficient and the performance degrades as the processes become more complex (as they do at nanoscale) and the designs get larger. On the other hand, a multi-engine architecture helps in a couple of ways - Uses a dedicated engine to optimally handle a particular memory circuit component and Provides an efficient infrastructure for managing and parallelizing the simulations.
The use of multiple, dedicated engines also results in the ability to produce greater performance in the simulation of embedded memory designs while increasing the accuracy of simulations.
Intelligent topological assessments
Recognizing an independent repeated structure or partition of a layout-extracted memory circuit, especially when there are millions of coupling caps and resistors, is tricky at best. Given that this dependence varies with input and resulting control signal changes, partitioning a circuit becomes all the more challenging. Algorithms that can intelligently recognize these partitions/memory topologies and appropriately guide the simulation to use these partitions are crucial to the speed and capacity of the fast Spice simulation.
Advanced interconnect evaluations
For embedded memory designs, parasitic loads are the predominant factor in signal delays and the numbers of parasitic elements outnumber active devices by a ratio over 4:1.
At the nanometer level, the composition of this interconnect is unique and complex. Dedicated algorithms have been developed that recognize these interconnect structures, model them accurately and simulate them efficiently. This is accomplished without affecting either the accuracy or the physical effects associated with that interconnect. This greatly enhances the speed of simulation as well as the capacity of the fast Spice simulator.
Conclusion
Embedded memory designers face an uphill task in design with several areas that are outside their realm of control. Escalating mask design complexity and cost severely limit design iterations. Newer methodologies will need to be adopted to streamline the design cycle. However, there are exciting developments on the embedded memory design simulation and verification front.
Fast Spice simulation technology designed to address the emerging challenges of nanometer designs greatly helps reduce the burden on the thankless designer. By having the high speed to accurately simulate the complex embedded memory structure, a novel technology such as this helps to drastically shorten the design cycle.
With its large capacity to rapidly verify chip-level netlists with parasitics, the next generation fast Spice simulator greatly improves the robustness of the design and reduces the time to market. If the embedded nanometer memory design challenges are to be tackled head-on, it is imperative for designers and design managers to seriously start considering the use of next generation fast Spice simulation and verification technologies into their design flows.
Current-based simulation
Active MOS devices are intrinsically current-based devices and a current-based model reflects this behavior significantly better than a voltage-based model. While a voltage-based model provides important information about transistor behavior, it has several drawbacks in terms of accuracy for current measurements, stability in simulations and size of the resulting matrix.
Current-based models are not only as accurate as Spice or Spice-like models, but they also simplify the topological structure of the equivalent circuits. This greatly improves the solution of non-linear equations and matrices. Additionally, current-based models are very efficient in device representation and require less memory than voltage-based models. This helps a great deal in addressing the large physical memory requirements when simulating large embedded memories.
Multi-engine architecture
An embedded memory circuit profile is unique in that it consists of digital, analog and mixed-signal blocks that closely interact with each other. Other features are the large replication of circuit structures and the small amount of active circuitry at any given clock cycle. The memory in itself can be decomposed into basic transistors, bit-cell blocks, decode blocks, interconnect structures and multiple other design entities that each share a unique simulation profile.
When considering a circuit for simulation, traditional fast Spice simulators use one monolithic engine to tackle all the varied elements in the circuit. This is inefficient and the performance degrades as the processes become more complex (as they do at nanoscale) and the designs get larger. On the other hand, a multi-engine architecture helps in a couple of ways - Uses a dedicated engine to optimally handle a particular memory circuit component and Provides an efficient infrastructure for managing and parallelizing the simulations.
The use of multiple, dedicated engines also results in the ability to produce greater performance in the simulation of embedded memory designs while increasing the accuracy of simulations.
Intelligent topological assessments
Recognizing an independent repeated structure or partition of a layout-extracted memory circuit, especially when there are millions of coupling caps and resistors, is tricky at best. Given that this dependence varies with input and resulting control signal changes, partitioning a circuit becomes all the more challenging. Algorithms that can intelligently recognize these partitions/memory topologies and appropriately guide the simulation to use these partitions are crucial to the speed and capacity of the fast Spice simulation.
Advanced interconnect evaluations
For embedded memory designs, parasitic loads are the predominant factor in signal delays and the numbers of parasitic elements outnumber active devices by a ratio over 4:1.
At the nanometer level, the composition of this interconnect is unique and complex. Dedicated algorithms have been developed that recognize these interconnect structures, model them accurately and simulate them efficiently. This is accomplished without affecting either the accuracy or the physical effects associated with that interconnect. This greatly enhances the speed of simulation as well as the capacity of the fast Spice simulator.
Conclusion
Embedded memory designers face an uphill task in design with several areas that are outside their realm of control. Escalating mask design complexity and cost severely limit design iterations. Newer methodologies will need to be adopted to streamline the design cycle. However, there are exciting developments on the embedded memory design simulation and verification front.
Fast Spice simulation technology designed to address the emerging challenges of nanometer designs greatly helps reduce the burden on the thankless designer. By having the high speed to accurately simulate the complex embedded memory structure, a novel technology such as this helps to drastically shorten the design cycle.
With its large capacity to rapidly verify chip-level netlists with parasitics, the next generation fast Spice simulator greatly improves the robustness of the design and reduces the time to market. If the embedded nanometer memory design challenges are to be tackled head-on, it is imperative for designers and design managers to seriously start considering the use of next generation fast Spice simulation and verification technologies into their design flows.
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